The present invention relates generally to the field of testing the quality and reliability of semiconductor chip assemblies (for example, wafer level semiconductor assemblies), and more particularly to testing the crackstop robustness of semiconductor assemblies.
Metallization layers are usually the top-most layers of semiconductor devices. The manufacturing of semiconductor devices is typically classified into two phases: the front end of line (FEOL) and the back end of line (BEOL). The BEOL phase starts at the point of the manufacturing process where metallization layers are formed. During the BEOL phase of manufacture of integrated circuit chips: (i) an intermediate sub-assembly, called a wafer (sometimes herein, a wafer level semiconductor assembly) is formed; (ii) the wafer undergoes laser scribing which introduces and/or propagates vertical and horizontal cracks; and (iii) the wafer level semiconductor assembly is “diced” (for example, by “die sawing”) to separate portions of the wafer to yield stock (herein referred to as “unprocessed chip assemblies) for multiple integrated circuit chips. The layers of the chip formed during the BEOL phase are sometimes herein referred to as “BEOL layers.” The unprocessed chip assemblies are typically subjected to further processing steps, (for example, packaging processing).
As mentioned above, the laser scribing or dicing processes can generate cracks that can damage active areas of the unprocessed chip assemblies yielded by the dicing. To prevent such damage by stopping the propagation of cracks, various kinds of structures are known to be used (for example, crackstop layers) at the perimeter locations of each chip within a wafer.